Computational lithography

Computational lithography (also known as computational scaling ) is the set of mathematical and algorithmic approaches designed to improve the resolution achievable through photolithography . Computational lithography has come to the forefront of photolithography in 2008 as the semiconductor industry grappled with the challenges associated with the transition to 22 nanometer CMOS process technology and beyond.

Context: industry forced to extend 193nm deep UV photolithography

The periodic enhancement in the resolution achieved through photolithography has been a driving force behind Moore’s Law . Resolution improvements enable printing of smaller geometries on an integrated circuit . The minimum feature size That a projection system Typically used in photolithography can print is Approximately Given by:



\ displaystyle \, CDis the minimum feature size (also called the critical dimension ).

\ displaystyle \, \ lambdais the wavelength of light used.

\ displaystyle \, NAis the digital aperture of the lens as seen from the wafer.

1(commonly called k1 factor ) is a coefficient that encapsulates process-related factors.

Historically, resolution enhancements in photolithography -have-been Achieved through the progression of stepper illumination sources to smaller and smaller Wavelengths – from “g-line” (436 nm) and “i-line” (365 nm) sources based are mercury lamps , to the current systems based on deep ultraviolet excimer laser sources at 193 nm. HOWEVER the progression to yet finer wavelength sources has-been stalled by the intractable problems associated with extreme ultraviolet lithography and x-ray lithography , forcing semiconductor manufacturers to extend the current 193 nm optical lithography systems up to Some form of next-generation lithographyProves viable (though 157 nm steppers have been marketed, they have proven cost-prohibitive at $ 50M each). [1] Efforts to improve resolution by increasing the density of lithography . As further improvements in resolution through wavelength reduction or increasing in numerical aperture have become either technically challenging or economically unfeasible, much attention has been paid to reducing the k1-factor. The factor can be reduced through process improvements, such as phase-shift photomasks . These technical-have enabled photolithography at the 32 nanometer CMOS process technology node using a wavelength of 193 nm (deep ultraviolet). However, with theITRS roadmap calling for the 22 nanometer node to be in use by 2011, photolithography researchers have had to develop an additional 22 nm manufacturing technology. [2] Computational lithography. Computing and lithography.

A short history of computational lithography

Computational lithography means the use of micro-lithography structures. Pioneering work was done by Chris Mack at NSA in developing PROLITH , Rick Dill at IBM and Andy Neureuther at University of California, Berkeley from the early 1980s. These tools were limited to lithography process optimization as the algorithms were limited to a few square micrometers of resist. Commercial full-chip optical proximity correction, using model forms, was first implemented by TMA (now a subsidiary of Synopsys ) and Numerical Technologies (also part of Synopsys) around 1997. [3]Since then the market and the complexity has grown significantly. With the move to sub-wavelength lithography at the 180 nm and 130 nm nodes, techniques such as Assist features, Phase Shift Masks started to be used together with OPC. For the transition from 65nm to 45nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn This predicted exponential increase in computational complexity for mask synthesis on the 45 nm process has spawned a significant venture capital investment in Design for Manufacturing start-up companies. [4]A number of startup companies promote their own disruptive solutions to this problem started to appear, techniques from custom hardware to acceleration to radical new algorithms such as reverse osmosis. Despite all this activity, incumbent OPC suppliers were able to adapt and retain their major customers, with RET and OPC being used together for previous nodes, algorithms and improvements in multi-core commodity processors. The term computational lithography was first used by Brion Technology (now a subsidiary of ASML ) in 2005 [5]to their hardware accelerated full chip lithography simulation platform. Since then the term has been used by the industry to describe full chip mask synthesis solutions. As 45 nm goes into full production and EUV lithography is delayed, 32 nm and 22 nm are expected to run on existing 193 nm scanners technology. Now, not only are they related to resurfacing capabilities, but also new computational lithography techniques such as Source Mask Optimization (SMO) is a better way to achieve better design. Today, all the major Mask Synthesis vendors have settled down to the term “Computational Lithography” to describe and promote the set of Mask Synthesis Technologies Required for 22 nm.

Techniques including computational lithography

Computational lithography makes use of a number of numerical simulations to improve the performance (resolution and contrast) of cutting-edge photomasks. The combined techniques include Resolution Enhancement Technology (RET), Optical Proximity Correction (OPC), Source Mask Optimization (SMO), and more. [6] The techniques vary in their technical feasibility and engineering sensitivity, resulting in the adoption of some and the continual R & D of others. [7]

Resolution Enhancement Technology (RET)

Resolution Enhancement Technology , first used in the 90 nanometer generation, using the mathematics of diffraction optics to specify multi-layer phase-shift photomasks that use interference patterns in the photomask that enhance resolution on the printed wafer surface.

Optical Proximity Correction (OPC)

Optical proximity correction uses computational methods to counteract the effects of diffraction-related blurring and under-exposure by modifying on-mask

  • geometries (a trace surrounded by a wide open area will be over-exposed compared with a dense pattern)
  • adding “dog-bone” to the end of lines to prevent line shortening
  • correcting for electron beam

OPC can be broadly divided into rule-based and model-based. [8] Inverse lithography technology, which treats the OPC as an inverse imaging problem, is also useful because it can provide unintuitive mask patterns. [9]

Complex modeling of the lens system and photoresist

Beyond the models used for RET and OPC, computational lithographics attempts to improve chip manufacturability and yields such as using the signature of the scanner to help improve the accuracy of the OPC model: [10]

  • polarization characteristics of the lens pupil
  • Jones matrix of the stepper lens
  • optical parameters of the photoresist stack
  • diffusion through the photoresist
  • stepper illumination control variables

A CPU-century worth of calculations or more

The computational effort behind these methods is immense. According to one estimate, the calculations required to be adjusted to 100-CPU-years of computer time. [11] dead link ] This does not include modeling the polarization of the photolithographic mask making flows. Brion Technologies, a subsidiary of ASML, the largest manufacturer of photolithography systems, markets a rack-mounted hardware accelerator dedicated to manufacturing computational lithographic calculations – a mask-making shop can buy a large number of their systems to run in parallel. Others have claimed significant acceleration using high-throughput graphics. [12]


  1. Jump up^ “Reticle enhancement technology will extend life of 193nm litho” ,Electronics Weekly , 2004-02-25
  2. Jump up^ Moretti, Gabe (2008-10-13), “Custom Litho Addresses 22-nm IC Manufacturing” , EETimes
  3. Jump up^ “Major US Semiconductor Choosing Maker TMA for OPC Software” ,PRNewswire , 1997-10-16
  4. Jump up^ McGrath, Dylan (2005-12-16), “DFM Pumps Up the Volume” ,EETimes
  5. Jump up^ McGrath, Dylan (2005-02-12), “Litho simulation vendor opens Japanese subsidiary” , EETimes
  6. Jump up^ LaPedus, Mark (2008-09-17), IBM Rolls Computational Scaling for Litho at 22-nm , EETimes
  7. Jump up^ E. Lam; A. Wong (2009), “Computation lithography: virtual reality and virtual virtuality” , Optics Express , 17 (15): 12259-12268, doi : 10.1364 / OE.17.012259 , PMID  19654627
  8. Jump up^ A. Wong (2001), Resolution enhancement techniques in optical lithography , SPIE Press
  9. Jump up^ S. Chan; A. Wong; E. Lam (2008), “Initialization for robust reverse synthesis of phase-shifting masks in optical projection lithography” ,Optics Express , 16 (19): 14746-14760, doi : 10.1364 / OE.16.014746
  10. Jump up^ Hand, Aaron (November 2006), “Nikon and Synopsys Deliver on Advanced OPC Promise” , Semiconductor International Check date values ​​in:( help ) |year= / |date= mismatch
  11. Jump up^ Wiley, Jim (May 2006), “Future challenges in computational lithography” , Solid State Technology
  12. Jump up^ LaPedus, Mark (2008-02-28), “Gauda OPC claims acceleration breakthrough.” , EE Times